A hardware accelerator having a memory (on-chip memory) on a same chip is used in a data-centric application represented by a deep neural network (DNN) or the like. The data-centric application requires a hardware accelerator having a large-capacity on-chip memory. However, a further improvement in the density of an SRAM (Static Random Access Memory) is considerably difficult.
It is known that the on-chip memory is mostly used for a FIFO (First-in First-out) memory. Therefore, an improvement in the density of the FIFO memory can also contribute to realization of a large-capacity on-chip memory.